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AD6645ASQ-105 数据表(PDF) 8 Page - Analog Devices |
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AD6645ASQ-105 数据表(HTML) 8 Page - Analog Devices |
8 / 24 page AD6645 Rev. D | Page 8 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. DNC = DO NOT CONNECT. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND. PIN 1 IDENTIFIER AD6645 TOP VIEW (Not to Scale) 1 DVCC 2 GND 3 VREF 4 GND 5 ENCODE 6 ENCODE 7 GND 8 AVCC 9 AVCC 10 GND 11 14 AIN 12 AIN 13 GND 15 16 17 18 19 20 21 22 23 24 25 26 27 GND 28 AVCC 29 GND 30 AVCC 31 DNC 32 OVR 33 DVCC 34 GND 35 DMID 36 D0 (LSB) 37 40 D1 38 D2 39 D3 41 42 43 44 45 46 47 48 49 50 51 52 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin Number Mnemonic Description 1, 33, 43 DVCC 3.3 V Power Supply (Digital) Output Stage Only. 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 GND Ground. 3 VREF 2.4 V Reference. Bypass to ground with a 0.1 μF microwave chip capacitor. 5 ENCODE Encode Input. Conversion initiated on rising edge. 6 ENCODE Complement of ENCODE, Differential Input. 8, 9, 14, 16, 18, 22, 26, 28, 30 AVCC 5 V Analog Power Supply. 11 AIN Analog Input. 12 AIN Complement of AIN, Differential Analog Input. 20 C1 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 24 C2 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 31 DNC Do not connect this pin. 32 OVR Overrange Bit. A logic level high indicates analog input exceeds ±FS. 35 DMID Output Data Voltage Midpoint. Approximately equal to (DVCC)/2. 36 D0 (LSB) Digital Output Bit (Least Significant Bit); Twos Complement. 37 to 41, 44 to 50 D1 to D5, D6 to D12 Digital Output Bits in Twos Complement. 51 D13 (MSB) Digital Output Bit (Most Significant Bit); Twos Complement. 52 DRY Data-Ready Output. 53 (EPAD) Exposed Paddle (EPAD) Exposed Pad. Connect the exposed pad to GND. |
类似零件编号 - AD6645ASQ-105 |
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类似说明 - AD6645ASQ-105 |
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