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CDC5801A 数据表(PDF) 9 Page - Texas Instruments |
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CDC5801A 数据表(HTML) 9 Page - Texas Instruments |
9 / 18 page CDC5801A LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 jitter specification over recommended operating free-air temperature range and VCC (unless otherwise noted) (continued) PARAMETER CLKOUT TEST CONDITIONS MIN TYP† MAX UNIT t(jitter) (Divider mode with phase alignment and MULT0:1 = 00 (Divider 50 MHz Period RMS (1 Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) 9 50 13 35 35 ps phase alignment and programmable delay features selected. See Figure 2.) (Divider ratio = 2) 62.5 MHz Period RMS (1 Σ jitter, full frequency band) Period p-p Phase jitter (accumulated, 12 kHz to 20 MHz) Cycle-to-cycle (+) Cycle-to-cycle (−) 6.5 30 10 26 26 ps † All typical values are at VDD = 3.3 V, TA = 25°C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT t(DC) Output duty cycle See Figure 3 45% 55% tr, tf Output rise and fall times (measured at 20%−80% of output voltage) See Figure 5 and Figure 1 150 350 ps † All typical values are at VDD = 3.3 V, TA = 25°C. |
类似零件编号 - CDC5801A |
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类似说明 - CDC5801A |
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