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ADP1706ACPZ-1.5-R7 数据表(PDF) 6 Page - Analog Devices

部件名 ADP1706ACPZ-1.5-R7
功能描述  1 A, Low Dropout, CMOS Linear Regulator
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1706ACPZ-1.5-R7 数据表(HTML) 6 Page - Analog Devices

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ADP1706/ADP1707/ADP1708
Rev. 0 | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
EN 1
GND 2
IN 3
IN 4
SS
8
SENSE
7
OUT
6
OUT
5
ADP1706
TOP VIEW
(Not to Scale)
ADP1706
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
1
EN
2
GND
3
IN
4
IN
7 SENSE
8SS
6OUT
5OUT
Figure 4. 8-Lead SOIC, ADP1706
Figure 5. 8-Lead LFCSP, ADP1706
EN 1
GND 2
IN 3
IN 4
TRK
8
SENSE
7
OUT
6
OUT
5
ADP1707
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
1
EN
2
GND
3
IN
4
IN
7SENSE
8TRK
6OUT
5OUT
TOP VIEW
(Not to Scale)
ADP1707
Figure 6. 8-Lead SOIC, ADP1707
Figure 7. 8-Lead LFCSP, ADP1707
EN 1
GND 2
IN 3
IN 4
ADJ
8
SENSE
7
OUT
6
OUT
5
ADP1708
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
1
EN
2
GND
3
IN
4
IN
7 SENSE
8 ADJ
6OUT
5OUT
ADP1708
TOP VIEW
(Not to Scale)
Figure 8. 8-Lead SOIC, ADP1708
Figure 9. 8-Lead LFCSP, ADP1708
Table 4. Pin Function Descriptions
ADP1706
Pin No.
ADP1707
Pin No.
ADP1708
Pin No.
Mnemonic
Description
1
1
1
EN
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the
regulator. For automatic startup, connect EN to IN.
2
2
2
GND
Ground.
3, 4
3, 4
3, 4
IN
Regulator Input Supply. Bypass IN to GND with a 4.7 μF or greater capacitor.
5, 6
5, 6
5, 6
OUT
Regulated Output Voltage. Bypass OUT to GND with a 4.7 μF or greater capacitor.
7
7
7
SENSE
Sense. Measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect
of IR drop between the regulator output and the load.
8
N/A
N/A
SS
Soft Start. A capacitor connected to this pin determines the soft start time.
N/A
8
N/A
TRK
Track. The output follows the voltage applied at the TRK pin. See the Theory of
Operation section for a more detailed description.
N/A
N/A
8
ADJ
Adjust. A resistor divider from OUT to ADJ sets the output voltage.
EP
EP
EP
EP
The exposed pad on the bottom of the SOIC package and the LFCSP package. EP
enhances thermal performance and is electrically connected to GND inside the
package. User is recommended to connect EP to the ground plane on the board.


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