AD1852

Rev. A | Page 8 of 20

Pin No.

Mnemonic

Input/Output

Description

25

LRCLK

I

Left/Right Clock Input for Serial Audio Data Input Port. This pin must run continuously.

26

BCLK

I

Bit Clock Input for Serial Audio Data Input Port. This pin need not run continuously; may be

gated or used in a burst fashion.

27

SDATA

I

Serial Audio Data Input, MSB First. Input for the serial audio data stream is as described the

in Serial Data Input Port section.

28

DVDD

I

Digital Power Supply. Connect this pin to the digital 5 V supply.

Table 12. Serial Data Input Mode

IDPM1 (Pin 20)

IDPM0 (Pin 21)

Serial Data Input Format

0

0

Right justified

0

1

1

0

Left justified

1

1

DSP

LEFT CHANNEL

RIGHT CHANNEL

LSB

MSB–2

LSB+2 LSB+1

MSB–1

MSB–2

MSB–1

MSB

LSB+2 LSB+1

LSB

MSB

LSB

BCLK

INPUT

SDATA

INPUT

LRCLK

INPUT

Figure 3. Right-Justified Mode

MSB–2

MSB–1

MSB

LSB+2 LSB+1

LSB

LEFT CHANNEL

RIGHT CHANNEL

BCLK

INPUT

SDATA

INPUT

LRCLK

INPUT

MSB

LSB

MSB–2

LSB+2 LSB+1

MSB–1

MSB

LEFT CHANNEL

RIGHT CHANNEL

BCLK

INPUT

SDATA

INPUT

LRCLK

INPUT

MSB–2

MSB–1

MSB

LSB+2

LSB+1

LSB

MSB

MSB–1

LSB

MSB–2

LSB+2

LSB+1

MSB–1

MSB

Figure 5. Left-Justified Mode

LEFT CHANNEL

RIGHT CHANNEL

BCLK

INPUT

SDATA

INPUT

LRCLK

INPUT

MSB–1

MSB

LSB+2

LSB+1

LSB

MSB

MSB–1

LSB

LSB+2 LSB+1

MSB–1

MSB

Figure 6. Left-Justified DSP Mode

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

MSB–1

MSB–2

LSB+2

LSB+1

MSB–1

MSB–2

MSB

LSB

LSB+2

LSB+1

MSB–1

LSB

MSB

BCLK

INPUT

SDATA

INPUT

LRCLK

INPUT