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AD667SD 数据表(PDF) 8 Page - Analog Devices |
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AD667SD 数据表(HTML) 8 Page - Analog Devices |
8 / 8 page AD667 REV. A –8– Right-justified data can be similarly accommodated. The over- lapping of data lines is reversed, and the address connections are slightly different. The AD667 still occupies two adjacent locations in the processor’s memory map. In the circuit of Fig- ure 9, location X01 loads the 8 LSBs and location X10 loads the 4 MSBs and updates the output. Figure 9. Right-Justified 8-Bit Bus Interface USING THE AD667 WITH 12- AND 16-BIT BUSES The AD667 is easily interfaced to 12- and 16-bit data buses. In this operation, all four address lines (A0 through A3) are tied low, and the latch is enabled by CS going low. The AD667 thus occupies a single memory location. This configuration uses the first and second rank registers simultaneously. The CS input can be driven from an active-low decoded address. It should be noted that any data bus activity during the period when CS is low will cause activity at the AD667 output. If data is not guaranteed stable during this period, the second rank register can be used to provide double buffering. Figure 10. Connections for 12- and 16-Bit Bus Interface OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Contact LCC (E) 28-Terminal Plastic Leaded Chip Carrier (P) 28-Pin Ceramic DIP (D) 28-Pin Plastic DIP (N) |
类似零件编号 - AD667SD |
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类似说明 - AD667SD |
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