数据搜索系统,热门电子元器件搜索 |
|
AD7943ARS-B 数据表(PDF) 5 Page - Analog Devices |
|
AD7943ARS-B 数据表(HTML) 5 Page - Analog Devices |
5 / 16 page AD7943/AD7945/AD7948 REV. B –5– (TA = TMIN to TMAX, unless otherwise noted) Limit @ Limit @ Parameter VDD = +3 V to +3.6 V VDD = +4.5 V to +5.5 V Units Description tSTB 2 60 40 ns min STB Pulsewidth tDS 15 10 ns min Data Setup Time tDH 35 25 ns min Data Hold Time tSRI 55 35 ns min SRI Data Pulsewidth tLD 55 35 ns min Load Pulsewidth tCLR 55 35 ns min CLR Pulsewidth tASB 0 0 ns min Min Time Between Strobing Input Shift Register and Loading DAC Register tSV 3 60 35 ns max STB Clocking Edge to SRO Data Valid Delay NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 µs on any digital input. 2STB mark/space ratio range is 60/40 to 40/60. 3t SV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. Specifications subject to change without notice. tSTB STB1, STB2, STB4 STB3 tDS tDH tSRI SRI DB11(N) (MSB) DB10(N) DB0(N) DB0(N–1) DB10(N–1) LD1, LD2, CLR SRO tSV tLD, tCLR tASB Figure 1. AD7943 Timing Diagram TO OUTPUT PIN CL 50pF 1.6mA IOL +2.1V IOH 200 A Figure 2. Load Circuit for Digital Output Timing Specifications AD7943 TIMING SPECIFICATIONS1 |
类似零件编号 - AD7943ARS-B |
|
类似说明 - AD7943ARS-B |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |