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CDCVF25081PWR 数据表(PDF) 6 Page - Texas Instruments

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部件名 CDCVF25081PWR
功能描述  3.3-V PHASED-LOCK LOOP CLOCK DRIVER
Download  16 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

CDCVF25081PWR 数据表(HTML) 6 Page - Texas Instruments

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CDCVF25081
3.3-V PHASED-LOCK LOOP CLOCK DRIVER
SCAS671A – OCTOBER 2001 – REVISED FEBRUARY 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
t(lock)
PLL lock time
f = 100 MHz
10
µs
t
Phase offset (CLKIN to FBIN)
f = 8 MHz to 66 MHz,
Vth = VDD/2 (see Note 5)
–200
200
ps
t(phoffset)
Phase offset (CLKIN to FBIN)
f = 66 MHz to 200 MHz,
Vth = VDD/2 (see Note 5)
–150
150
ps
tPLH
Low-to-high level output propagation delay
S2 = High,
S1 = Low (PLL bypass)
2.5
6
ns
tPHL
High-to-low level output propagation delay
S2 = High,
S1 = Low (PLL by ass)
f = 1 MHz,
CL = 25 pF
tsk(o)
Output skew (Yn to Yn) (see Note 4)
150
ps
t
Part to part skew
S2 = high,
S1 = high (PLL mode)
600
ps
tsk(pp)
Part-to-part skew
S2 = high,
S1 = low (PLL bypass)
700
ps
f = 66 MHz to 200 MHz, CL = 15 pF
±100
tjit(cc)
Jitter (cycle-to-cycle)
f = 66 MHz to 100 MHz, CL = 25 pF
f = 8 MHz to 66 MHz (see Figure 6)
±150
ps
odc
Output duty cycle
f = 8 MHz to 200 MHz
43%
57%
tsk(p)
Pulse skew
S2 = High,
S1 = low (PLL bypass)
f = 1 MHz,
CL = 25 pF
0.7
ns
t
Rise time rate
CL = 15 pF,
See Figure 4
0.8
3.3
V/ns
tr
Rise time rate
CL = 25 pF,
See Figure 4
0.5
2
V/ns
t
Fall time rate
CL = 15 pF,
See Figure 4
0.8
3.3
V/ns
tf
Fall time rate
CL = 25 pF,
See Figure 4
0.5
2
V/ns
† All typical values are at respective nominal VDD.
NOTES:
4. The tsk(o) specification is only valid for equal loading of all outputs.
5. Similar waveform at CLKIN and FBIN are required. For phase displacement between CLKIN and Y-outputs see Figure 5.


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