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AD7742BN 数据表(PDF) 2 Page - Analog Devices

部件名 AD7742BN
功能描述  Single and Multichannel, Synchronous Voltage-to-Frequency Converters
Download  12 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7742BN 数据表(HTML) 2 Page - Analog Devices

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REV. 0
–2–
AD7741–SPECIFICATIONS
(VDD = +4.75 V to +5.25 V; VREF = +2.5 V; fCLKIN = 6.144 MHz; all specifications TMIN to
TMAX unless otherwise noted.)
B and Y Version
1
Parameter
2
Min
Typ
Max
Units
Conditions/Comments
DC PERFORMANCE
Integral Nonlinearity
fCLKIN = 200 kHz
3
±0.012
% of Span
4
fCLKIN = 3 MHz
3
±0.012
% of Span
fCLKIN = 6.144 MHz
±0.024
% of Span
VDD > 4.8 V
Offset Error
±40
mV
Gain Error
0
+0.8
+1.6
% of Span
Offset Error Drift
3
±30
µV/°C
Gain Error Drift
3
±16
ppm of Span/
°C
Power Supply Rejection Ratio
3
–63
dB
∆V
DD =
±5%
ANALOG INPUT
5
Input Current
±50
±100
nA
Input Voltage Range
0
VREF
V
+2.5 V REFERENCE (REFIN/OUT)
REFIN
Nominal Input Voltage
2.5
V
Input Impedance
6
N/A
REFOUT
Output Voltage
2.38
2.50
2.60
V
Output Impedance
3
1k
Reference Drift3
±50
ppm/
°C
Line Rejection
–60
dB
Reference Noise (0.1 Hz to 10 Hz)
3
100
µV p-p
LOGIC OUTPUT
Output High Voltage, VOH
4.0
V
Output Sourcing 800
µA7
Output Low Voltage, VOL
0.4
V
Output Sinking 1.6 mA
7
Minimum Output Frequency
0.05 fCLKIN
Hz
VIN = 0 V
Maximum Output Frequency
0.45 fCLKIN
Hz
VIN = VREF
LOGIC INPUT
PD ONLY
Input High Voltage, VIH
2.4
V
Input Low Voltage, VIL
0.8
V
Input Current
±100
nA
Pin Capacitance
6
10
pF
CLKIN ONLY
Input High Voltage, VIH
3.5
V
Input Low Voltage, VIL
0.8
V
Input Current
±2
µA
Pin Capacitance
6
10
pF
CLOCK FREQUENCY
Input Frequency
6.144
MHz
For Specified Performance
POWER REQUIREMENTS
VDD
4.75
5.25
V
IDD (Normal Mode)
8
mA
Output Unloaded
IDD (Power-Down)
15
35
µA
Power-Up Time
3
30
µs
Coming Out of Power-Down Mode
NOTES
1Temperature ranges: B Version –40
°C to +85°C: Y Version: –40°C to +105°C.
2See Terminology.
3Guaranteed by design and characterization, not production tested.
4Span = Maximum Output Frequency–Minimum Output Frequency.
5The absolute voltage on the input pin must not go more positive than V
DD – 2.25 V or more negative than GND.
6Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400
µA in order to overdrive the internal reference.
7These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
Specifications subject to change without notice.


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