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SI3019-F-GT 数据表(PDF) 1 Page - Silicon Laboratories |
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SI3019-F-GT 数据表(HTML) 1 Page - Silicon Laboratories |
1 / 112 page Rev. 1.31 5/09 Copyright © 2009 by Silicon Laboratories Si3050 + Si3018/19 Si3050 + Si3018/19 GLOBAL VOICE DAA Features Applications Description The Si3050+Si3018/19 Voice DAA chipset provides a highly-programmable and globally-compliant foreign exchange office (FXO) analog interface that is ideal for DSL IADs, PBXs, IP-PBXs, and VoIP gateway products. The solution implements Silicon Laboratories' patented isolation capacitor technology, which eliminates the need for costly isolation transformers, relays, or opto-isolators, while providing superior surge immunity for robust field performance. The Voice DAA is available in one 20-pin TSSOP (Si3050) and one 16-pin TSSOP/SOIC (Si3018/19) and requires minimal external components. The Si3050 interfaces directly to standard telephony PCM interfaces. Functional Block Diagram PCM highway data interface µ-law/A-law companding SPI control interface GCI interface 80 dB dynamic range TX/RX Line voltage monitor Loop current monitor +6 dBm or +3.2 dBm TX/RX level mode Parallel handset detection 3 µA on-hook line monitor current Overload detection Programmable line interface AC termination DC termination Ring detect threshold Ringer impedance TIP/RING polarity detection Integrated codec and 2- to 4-wire analog hybrid Programmable digital hybrid for near-end echo reduction Polarity reversal detection Programmable digital gain in 0.1 dB increments Integrated ring detector Type I and II caller ID support Pulse dialing support 3.3 V power supply Daisy-chaining for up to 16 devices Greater than 5000 V isolation Patented isolation technology Ground start and loop start support Available in Pb-free RoHS-compliant packages DSL IADs VoIP gateways PBX and IP-PBX systems Voice mail systems Hybrid, AC and DC Terminations Ring Detect Off-Hook IB SC DCT VREG2 DCT2 DCT3 RNG1 RNG2 QB QE QE2 RX Si3018/19 VREG Si3050 Control Data Interface Isolation Interface CS SCLK SDI SDO SDI THRU Control Logic PCLK DTX DRX FSYNC Line Data Interface RG TGD TGDE RESET AOUT/INT RGDT Isolation Interface US Patent# 5,870,046 US Patent# 6,061,009 Other Patents Pending Ordering Information See page 102. Pin Assignments Si3050 Si3018/19 2 1 3 4 5 6 7 8 15 16 14 13 12 11 9 10 19 20 18 17 FSYNC SCLK PCLK SDI SDO AOUT/INT RG DTX DRX V A C1A C2A SDITHRU RESET GND TGDE TGD CS RGDT V DD QE DCT RX IB C1B C2B VREG RNG1 DCT2 DCT3 QB QE2 SC VREG2 RNG2 IGND 2 1 3 4 5 6 7 8 15 16 14 13 12 11 10 9 |
类似零件编号 - SI3019-F-GT |
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类似说明 - SI3019-F-GT |
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