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74HC273D-Q100 数据表(PDF) 10 Page - NXP Semiconductors |
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74HC273D-Q100 数据表(HTML) 10 Page - NXP Semiconductors |
10 / 19 page 74HC_HCT273_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 19 June 2013 10 of 19 NXP Semiconductors 74HC273-Q100; 74HCT273-Q100 Octal D-type flip-flop with reset; positive-edge trigger 11. Waveforms Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay clock input (CP) to output (Qn), clock (CP) pulse width, output transition time and the maximum clock pulse frequency 001aae062 CP input Qn output tPHL tPLH tW tW VM 10% 90% VOH VI GND VOL VM VM 1/fmax tTHL tTLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Propagation delay master reset (MR) to output (Qn), pulse width master reset (MR) and recovery time master reset (MR) to clock (CP) mna464 MR input CP input Qn output tPHL tW trec VM VI GND VI VOL GND VM VM VOH |
类似零件编号 - 74HC273D-Q100 |
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类似说明 - 74HC273D-Q100 |
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