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ML4819CP 数据表(PDF) 7 Page - Fairchild Semiconductor

部件名 ML4819CP
功能描述  Power Factor and PWM Controller ?쏞ombo?
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
标志 FAIRCHILD - Fairchild Semiconductor

ML4819CP 数据表(HTML) 7 Page - Fairchild Semiconductor

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ML4819
REV. 1.0 10/10/2000
7
SLOPE COMPENSATION
Slope compensation is accomplished by adding 1/2 of the
current flowing out of pin 12 to pin 1 (for the PFC section
and pin 9 (for the PWM section). The amount of slope
compensation is equal to (IRAMP COMP/2) × RL where RL is
the impedance to GND on pin 1 or pin 9. Since most of
the PWM applications will be limited to 50% duty cycle,
slope compensation should not be needed for the PWM
section. This can be defeated by using a low impedance
load to the current sense on pin 9.
500
400
300
200
100
0
0
100
200
300
400
500
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
1. 5V
SINE INPUT CURRENT (µA)
Figure 8. Gain Modulator Linearity
ENABLE
VREF
VREF
GEN.
9V
INTERNAL
BIAS
5V VREF
VCC
+
Figure 9. Under-Voltage Lockout Block Diagram
TA = 25 C
40
30
20
10
0
0
102030
40
VCC, SUPPLY VOLTAGE (V)
Figure 10a. Total Supply Current vs. Supply Voltage
START-UP
25
30
35
20
15
10
5
0
0
1020
30405060
70
TEMPERATURE ( C)
OPERATING
CURRENT
Figure 10b. Supply Current (ICC) vs. Temperature
OSC
10
20
12
RT
RSC
VREF
IR(SC)
TO PIN 9
TO PIN 1
IR(SC)
2
IR(SC)
2
9V
CT
RAMP COMP
SLOPE
COMPENSATION
Q1
Figure 7. Slope Compensation Circuit
UNDER VOLTAGE LOCKOUT
On power-up the ML4819 remains in the UVLO condition;
output low and quiescent current low. The IC becomes
operational when VCC reaches 16V. When VCC drops
below 10V, the UVLO condition is imposed. During the
UVLO condition, the 5V VREF pin is “off”, making it
usable as a status flag.


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