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ML4818CP 数据表(PDF) 6 Page - Fairchild Semiconductor |
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ML4818CP 数据表(HTML) 6 Page - Fairchild Semiconductor |
6 / 13 page PRODUCT SPECIFICATION ML4818 REV. 1.0.3 6/21/01 6 Functional Description Phase Modulator Power is controlled by modulating the switching phase on sides A and B of the full H-bridge converter (Figure 1). Power is delivered to the output through the transformer sec- ondary. The power conversion process is described by the following sequence and illustrated by the timing diagram of Figure 2: 1. A2 and B1 are high (Q1 and Q2 are on), beginning the power conversion cycle. 2. After the Φ MOD comparator trips, B1 goes low turning off Q2. The parasitic drain-to-source capacitances of Q2 and Q4 charge to +VIN. This forces the drain-to-source voltage across Q3 to 0V. 3. B2 now goes high after tDELAY (set by RDELAY). Since the voltage across Q3 is now 0V, B2 turns Q3 on at zero voltage. 4. The CLOCK now goes high turning A2 off. During this period, Q1 and Q2 and Q4 are off. The transformer leak- age current discharges the drain-to-source capacitance on Q4 until there is 0V across it. 5. A1 will remain low for a period defined by tDELAY, then it goes high. The voltage across Q4 is now 0V as A1 turns it on at zero voltage. 6. The previous sequence is now repeated with the oppo- site polarity on all outputs (see Figure 2). The above sequence is then repeated but with the opposite polarity on all outputs. Figure 1. Simplified diagram of Phase Modulated power Outputs Figure 2. Phase Modulation control waveforms (Shaded areas indicate a power cycle) B2 B1 A2 A1 ILIM RSENSE TB Q3 Q2 Q4 Q1 TA TRANSFORMER L LEAKAGE B A +VIN ML4818 tDELAY tDELAY tDELAY tDELAY tDELAY tPD1 tPD1 tDELAY tPD1 CT CLOCK A2 A1 B1 B2 B A |
类似零件编号 - ML4818CP |
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类似说明 - ML4818CP |
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