ML4804

REV. 1.0.2 3/9/2001

11

No voltage error amplifier is included in the PWM stage of

the ML4804, as this function is generally performed on the

output side of the PWM’s isolation boundary. To facilitate

the design of optocoupler feedback circuitry, an offset has

been built into the PWM’s RAMP 2 input which allows

voltages below 1.25V.

PWM Current Limit

current limiter for the PWM section. Should the input

voltage at this pin ever exceed 1V, the output of the PWM

will be disabled until the output flip-flop is reset by the

clock pulse at the start of the next PWM power cycle.

than its nominal 2.45V. Once this voltage reaches 2.45V,

which corresponds to the PFC output capacitor being

charged to its rated boost voltage, the soft-start begins.

PWM Control (RAMP 2)

When the PWM section is used in current mode, RAMP 2

is generally used as the sampling point for a voltage

representing the current in the primary of the PWM’s

output transformer, derived either by a current sensing

resistor or a current transformer. In voltage mode, it is the

input for a ramp voltage generated by a second set of

minimum value of zero volts and should have a peak

value of approximately 5V. In voltage mode operation,

feedforward from the PFC output buss is an excellent way

to derive the timing ramp for the PWM stage.

Soft Start

Start-up of the PWM is controlled by the selection of the

external capacitor at SS. A current source of 25

µA

supplies the charging current for the capacitor, and start-

up of the PWM begins at 1.25V. Start-up delay can be

programmed by the following equation:

(6)

It is important that the time constant of the PWM soft-start

allow the PFC time to generate sufficient output power for

the PWM section. The PWM start-up delay should be at

least 5ms.

(6a)

Caution should be exercised when using this minimum

soft start capacitance value because premature charging of

the SS capacitor and activation of the PWM section can

related both to line voltage and nominal PFC output

voltage. Typically, a 1.0

µF soft start capacitor will allow

prior to activation of the PWM section at line voltages

between 90Vrms and 265Vrms.

Figure 4. Typical Trailing Edge Control Scheme

RAMP

VEAO

TIME

VSW1

TIME

REF

EA

–

+

–

+

OSC

DFF

R

D

Q

Q

CLK

U1

RAMP

CLK

U4

U3

C1

RL

I4

SW2

SW1

+

DC

I1

I2

I3

VIN

L1

U2

Ct

A

V

SS

DELAY

=× 25

125

µ

.

Cms

A

V

nF

=

5

25

125

100

µ

.