数据搜索系统,热门电子元器件搜索 |
|
ML4801CS 数据表(PDF) 10 Page - Fairchild Semiconductor |
|
ML4801CS 数据表(HTML) 10 Page - Fairchild Semiconductor |
10 / 14 page ML4801 10 REV. 1.1 3/9/2001 LEADING/TRAILING MODULATION Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 3 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 4 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method. TYPICAL APPLICATIONS Figure 9 is the application circuit for a complete 100W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 33. REF EA – + – + OSC DFF R D Q Q CLK U1 RAMP CLK U4 U3 C1 RL I4 SW2 SW1 + DC I1 I2 I3 VIN L1 VEAO CMP U2 RAMP VEAO TIME VSW1 TIME Figure 4. Leading/Trailing Edge Control Scheme Figure 3. Typical Trailing Edge Control Scheme RAMP VEAO TIME VSW1 TIME REF EA – + – + OSC DFF R D Q Q CLK U1 RAMP CLK U4 U3 C1 RL I4 SW2 SW1 + DC I1 I2 I3 VIN L1 U2 |
类似零件编号 - ML4801CS |
|
类似说明 - ML4801CS |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |