Arizona Microtek, Inc.

AZT71

Programmable Capacitive Tuning IC

www.azmicrotek.com

+1-480-962-5881

8

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Jan 2013, Rev 1.3

t

DA

CLK

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

bit 9

bit 10

bit 0

bit 10

loaded last

PV

4µs

min

10ms

min

≥5.6V,

≤6.1V

Figure 11 – Second programming cycle to program bit4 into the EEPROM

During programming, the PV pin is used to program the necessary control bits into the EEPROM. However, it is also used

to read the bits currently programmed into the EEPROM. When the PV pin is not used during programming, the AZT71

provides a weak pull-up and pull-down on the pin. This allows the EEPROM data to be shifted out to the PV pin and read

after the CLK sequence is complete and when the DA & CLK pins are high (Figure 12). Each EEPROM bit is selected by

setting the DA signal low (EEPROM selection is active low) during the CLK sequence. With an external 68kΩ resistor

on the PV pin, a low EEPROM bit produces ≤ 0.4V level while a high EEPROM bit produces a ≥ 0.6*V

DD

level.

t

DA

CLK

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

bit 9

bit 10

bit0

bit10

loaded last

PV

≥ 0.6*V

DD

bit5

selected

Resulting voltage if

bit5 was high in

EEPROM

Resulting voltage if

bit5 was low in

EEPROM

≤ 0.4V

indeterminate

With an external 68k

Ω resistor pull-up to V

DD

Figure 12 – Timing diagram to read bits from EEPROM