AN-1039

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity

by Eamon Nash

Rev. 0 | Page 1 of 8

INTRODUCTION

The in-phase and quadrature modulator (IQ modulator) is a

key component in modern wireless transmitters. It provides a

convenient method for modulating data bits or symbols onto

an RF carrier. IQ upconversion has become the architecture

of choice for implementing transmitter signal chains for end

applications such as cellular, WiMAX, and wireless point-to-

point. IQ modulators, however, can degrade signal fidelity in

ways that are somewhat unique. These effects can degrade the

quality of the transmitted signal during the modulation process,

resulting in degraded error vector magnitude (EVM) at the

receiver, which in turn degrades bit error rate (BER). Fortu-

nately, algorithms exist that can correct these imperfections.

This application note describes a typical zero-IF or direct-

conversion transmitter and provides a brief introduction to

digital modulation. Other items discussed are: the imper-

fections introduced by the modulator are examined with

particular focus on the effect of temperature and frequency

changes, in-factory and in-field algorithms that can reduce the

effect of these modulator imperfections is also discussed, and

particular focus is placed on the efficacy of in-factory set-and-

forget algorithms.

A TYPICAL WIRELESS TRANSMITTER

Figure 1 shows a block diagram of a direct-conversion wireless

transmitter that uses an IQ modulator to modulate a bit stream

onto a carrier. A single bit stream is split into two parallel bit

streams at half the original data rate. To limit the spectral band-

width of the final carrier, the two bit streams are low-pass filtered

in the digital domain. To do this, the original bit-streams must

be digitally oversampled by the digital signal processor or field

programmable gate array (FPGA). So, instead of two bit streams,

there are now two streams of digital words. The chosen resolu-

tion of these words depends upon multiple factors such as the

required signal-to-noise ratio of the link and the chosen mod-

ulation scheme (QPSK in this case). Word widths between 12

and 16 bits are commonly chosen.

AD8363

50dB RMS

DETECTOR

SPECTRUM

ANALYZER

AD8352

FPGA OR DSP

DIGITAL

DEMOD

1.5

1.0

2.0

TIME (msec)

–600

–400

–200

0

200

400

600

–800

800

–600

–400

–200

0

200

400

600

–800

800

–600

–400

–200

0

200

400

600

–800

800

–600

–400

–200

0

200

400

600

–800

800

1.5

1.0

2.0

TIME (msec)

–600

–400

–200

200

0

400

600

–800

800

1.829

1.329

2.329

TIME (msec)

OVERSAMPLE

LOW-PASS

FILTER

OVERSAMPLE

LOW-PASS

FILTER

AD9230

HPA

ADL5320

50

Ω

50

Ω

0°

90°

100

Ω

100

Ω

LOW-

PASS

FILTER

LOW-

PASS

FILTER

GAIN

DAC 1

AUX

DAC1

16-BIT

I DAC

PHASE

ADJUST

AD9788

ADL5375

AUX

DAC2

GAIN

DAC 2

16-BIT

Q DAC

PHASE

ADJUST

I

Q

DIGITAL

FILTER

DIGITAL

FILTER

Figure 1. A Zero IF Direct-Conversion Transmitter with Optional Loop-Back Receiver