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Si5328C-C-GM 数据表(PDF) 11 Page - Silicon Laboratories |
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Si5328C-C-GM 数据表(HTML) 11 Page - Silicon Laboratories |
11 / 70 page Si5328 Rev. 1.0 11 PLL Performance (fin = fout = 346 MHz; BW = 0.088 Hz; LVPECL) Lock Time1 tLOCKMP Start of ICAL to LOL low, LOCKT = 4, FASTLOCK enabled —2 — s Start of ICAL to LOL low, LOCKT = 1, FASTLOCK enabled —12.5 — s Settle Time1 tSETTLE Start of ICAL to output phase within 45 degrees of final value, LOCKT = 4, FASTLOCK enabled —1 — s Start of ICAL to output phase within 45 degrees of final value, LOCKT = 1, FASTLOCK enabled —1 — s Output Clock Phase Change tP_STEP After clock switch f3 128 kHz —200 — ps Closed Loop Jitter Peaking JPK —0.05 0.2 dB Jitter/Wander Tolerance2 JTOL Jitter Frequency Loop Bandwidth 5000/BW — — ns pk-pk Phase Noise fout = 156.25 MHz CKOPN 1 kHz Offset — –120 — dBc/Hz 10 kHz Offset — –128 — dBc/Hz 100 kHz Offset — –130 — dBc/Hz 1 MHz Offset — –144 — dBc/Hz Subharmonic Noise SPSUBH Phase Noise @ 100 kHz Offset —–88 — dBc Spurious Noise SPSPUR Max spur @ n x F3 (n 1, n x F3 < 100 MHz) —–93 — dBc Table 3. AC Characteristics (Continued) (VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Silicon Labs for further details. 2. See Section 9 of “AN775: Si5328 Synchronous Ethernet Compliance Test Report” for more details. |
类似零件编号 - Si5328C-C-GM |
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类似说明 - Si5328C-C-GM |
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