TD9944

Features

Dual N-channel devices

Low threshold – 2.0V max.

High input impedance

Low input capacitance – 125pF max.

Fast switching speeds

Low on-resistance

Free from secondary breakdown

Low input and output leakage

Applications

Logic level interfaces – ideal for TTL and CMOS

Solid state relays

Battery operated systems

Photo voltaic drives

Analog switches

General purpose line drivers

Telecom switches

►

►

►

►

►

►

►

►

►

►

►

►

►

►

►

General Description

This low threshold, enhancement-mode (normally-off)

transistor utilizes a vertical DMOS structure and Supertex’s

well-proven, silicon-gate manufacturing process. This

combination produces a device with the power handling

capabilities of bipolar transistors and the high input

impedance and positive temperature coefficient inherent

in MOS devices. Characteristic of all MOS structures, this

device is free from thermal runaway and thermally-induced

secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications where

very low threshold voltage, high breakdown voltage, high

input impedance, low input capacitance, and fast switching

speeds are desired.

Dual N-Channel Enhancement-Mode

Vertical DMOS FET

Absolute Maximum Ratings

Parameter

Value

Drain-to-source voltage

BV

DSS

Drain-to-gate voltage

BV

DGS

Gate-to-source voltage

±20V

Operating and storage temperature

Soldering temperature*

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

*

Distance of 1.6mm from case for 10 seconds.

Ordering Information

Device

Package Option

BV

(V)

R

DS(ON)

(max)

(Ω)

I

D(ON)

(min)

(A)

V

GS(th)

(max)

(V)

8-Lead SOIC

4.90x3.90mm body

1.75mm height (max)

1.27mm pitch

TD9944

TD9944TG-G

240

6.0

1.0

2.0

-G indicates package is RoHS compliant (‘Green’)

G2

S2

G1

S1

D2

D2

D1

D1

YY = Year Sealed

WW = Week Sealed

= “Green” Packaging

T D 9 9

4 4 T G

Y Y W W

8-Lead SOIC (TG)

Product Marking

8-Lead SOIC (TG)

Package may or may not include the following marks: Si or

Pin Configuration