Data Sheet

AD7091R

Rev. 0 | Page 5 of 20

TIMING SPECIFICATIONS

Table 2.

Parameter

Unit

Description

50

MHz max

Frequency of serial read clock

8

ns max

Delay from the end of a conversion until SDO three-state is disabled

7

ns max

Data access time after SCLK falling edge

ns min

SCLK high pulse width

3

ns min

SCLK to data valid hold time

ns min

SCLK low pulse width

15

ns max

SCLK falling edge to SDO high impedance

10

ns min

CONVST pulse width

650

ns max

Conversion time

6

ns min

18

ns max

Delay from

8

ns min

8

ns min

Delay from the end of a conversion until

50

ms typ

Power-up time with internal reference2

100

µs max

Power-up time with external reference

50

ns min

Time between last SCLK edge and next CONVST pulse

1

Sample tested during initial release to ensure compliance.

2

With a 2.2 µF reference capacitor.