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AD7568BP-REEL 数据表(PDF) 3 Page - Analog Devices |
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AD7568BP-REEL 数据表(HTML) 3 Page - Analog Devices |
3 / 14 page AD7568 –3– TIMING SPECIFICATIONS Limit at Limit at Parameter TA = +25 CTA = –40 C to +85 C Units Description t1 100 100 ns min CLKIN Cycle Time t2 40 40 ns min CLKIN High Time t3 40 40 ns min CLKIN Low Time t4 30 30 ns min FSIN Setup Time t5 30 30 ns min Data Setup Time t6 5 5 ns min Data Hold Time t7 90 90 ns min FSIN Hold Time t8 2 70 70 ns max SDOUT Valid After CLKIN Falling Edge t9 40 40 ns min LDAC , CLR Pulse Width NOTES 1Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2t 8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. CLKIN (I) SDIN (I) SDOUT (O) DB15 DB0 DB15 DB0 FSIN (I) LDAC, CLR t1 t4 t 7 t2 t 3 t 6 t 5 t 8 t 9 NOTES 1. AO IS HARDWIRED HIGH OR LOW. Figure 1. Timing Diagram (VDD = +5 V 5%; IOUT1 = IOUT2 = 0 V; TA = TMIN to TMAX, unless otherwise noted) 1.6mA I OL +2.1V I OH 200 µA C L 50pF TO OUTPUT PIN Figure 2. Load Circuit for Digital Output Timing Specifications REV. C |
类似零件编号 - AD7568BP-REEL |
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类似说明 - AD7568BP-REEL |
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