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AD7277 数据表(PDF) 7 Page - Analog Devices |
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AD7277 数据表(HTML) 7 Page - Analog Devices |
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7 / 28 page  AD7273/AD7274 Rev. 0 | Page 7 of 28 TIMING SPECIFICATIONS VDD = 2.35 V to 3.6 V; VREF = 2.35 to VDD; TA = TMIN to TMAX, unless otherwise noted.1 Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Table 4. Parameter Limit at TMIN, TMAX AD7273/AD7274 Unit Description fSCLK2 500 kHz min3 48 MHz max tCONVERT 14 × tSCLK AD7274 12 × tSCLK AD7273 tQUIET 4 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 3 ns min Minimum CS pulse width t2 6 ns min CS to SCLK setup time t34 4 ns max Delay from CS until SDATA three-state disabled t44 15 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK low pulse width t6 0.4 tSCLK ns min SCLK high pulse width t74 5 ns min SCLK to data valid hold time t8 14 ns max SCLK falling edge to SDATA three-state 5 ns min SCLK falling edge to SDATA three-state t9 4.2 ns max CS rising edge to SDATA three-state tPOWER-UP5 1 μs max Power-up time from full power-down 1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 The time required for the output to cross the VIH or VIL voltage. 5 See the Power-Up Times section SCLK VIH VIL SDATA t4 Figure 2. Access Time After SCLK Falling Edge SCLK VIH VIL SDATA t7 Figure 3. Hold Time After SCLK Falling Edge SCLK 1.4V SDATA t8 Figure 4. SCLK Falling Edge SDATA Three-State |
类似零件编号 - AD7277 |
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类似说明 - AD7277 |
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