数据搜索系统,热门电子元器件搜索 |
|
AD1853JRSZ 数据表(PDF) 5 Page - Analog Devices |
|
AD1853JRSZ 数据表(HTML) 5 Page - Analog Devices |
5 / 16 page REV. A AD1853 –5– PIN FUNCTION DESCRIPTIONS Pin Input/Output Pin Name Description 1I DGND Digital Ground. 2I MCLK Master Clock Input. Connect to an external clock source. See Table II for allowable frequencies. 3I CLATCH Latch input for control data. This input is rising-edge sensitive. 4I CCLK Control clock input for control data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. 5I CDATA Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying control information and channel-specific attenuation. 6I INT4 × Assert HI to select interpolation ratio of 4 ×, for use with double-speed inputs (88 kHz or 96 kHz). Assert LO to select 8 × interpolation ratio. 7I INT2 × Assert HI to select interpolation ratio of 2 ×, for quad-speed inputs (176 kHz or 192 kHz). Assert LO to select 8 × interpolation ratio. 8O ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal input for more than 1024 LR Clock Cycles. 9I DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to impose a 50 µs/15 µs response characteristic on the output audio spectrum at an assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via SPI control register. 10 I IREF Connection point for external bias resistor. Voltage held at VREF. 11 I AGND Analog Ground. 12 O OUTL+ Left Channel Positive line level analog output. 13 O OUTL– Left Channel Negative line level analog output. 14 O FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer- ence with parallel 10 µF and 0.1 µF capacitors to the AGND (Pin 11). 15 I FCR Filter cap return pin for cap connected to FILTB (Pin 19). 16 O OUTR– Right Channel Negative line level analog output. 17 O OUTR+ Right Channel Positive line level analog output. 18 I AVDD Analog Power Supply. Connect to analog +5 V supply. 19 O FILTB Filter Capacitor connection, connect 10 µF capacitor to FCR (Pin 15). 20 I IDPM1 Input serial data port mode control one. With IDPM0, defines one of four serial modes. 21 I IDPM0 Input serial data port mode control zero. With IDPM1, defines one of four serial modes. 22 O ZEROL Left Channel Zero Flag output. This pin goes HI when Left Channel has no signal input for more than 1024 LR Clock Cycles. 23 I MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation. 24 I RST Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is reset on the rising edge of this signal. The serial control port registers are reset to the default values. Connect HI for normal operation. 25 I L/ RCLK Left/ Right clock input for input data. Must run continuously. 26 I BCLK Bit clock input for input data. 27 I SDATA Serial input, MSB first, containing two channels of 16/18/20/24 bit twos-complement data. 28 I DVDD Digital Power Supply Connect to digital +5 V supply. |
类似零件编号 - AD1853JRSZ |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |