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AD9279-65EBZ 数据表(PDF) 1 Page - Analog Devices |
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AD9279-65EBZ 数据表(HTML) 1 Page - Analog Devices |
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1 / 44 page  Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator AD9279 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. FEATURES 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator Low power: 141 mW per channel, TGC mode, 40 MSPS; 60 mW per channel, CW mode 10 mm × 10 mm, 144-ball CSP-BGA TGC channel input-referred noise: 0.8 nV/ √Hz, max gain Flexible power-down modes Fast recovery from low power standby mode: <2 μs Overload recovery: <10 ns Low noise preamplifier (LNA) Input-referred noise: 0.75 nV/√Hz, gain = 21.3 dB Programmable gain: 15.6 dB/17.9 dB/21.3 dB 0.1 dB compression: 1000 mV p-p/ 750 mV p-p/450 mV p-p Dual-mode active input impedance matching Bandwidth (BW): >100 MHz Variable gain amplifier (VGA) Attenuator range: −45 dB to 0 dB Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB Linear-in-dB gain control Antialiasing filter (AAF) Programmable second-order LPF from 8 MHz to 18 MHz Programmable HPF Analog-to-digital converter (ADC) SNR: 70 dB, 12 bits up to 80 MSPS Serial LVDS (ANSI-644, low power/reduced signal) CW mode I/Q demodulator Individual programmable phase rotation Output dynamic range per channel: >160 dBc/√Hz Output-referred SNR: 155 dBc/√Hz, 1 kHz offset, −3 dBFS GENERAL DESCRIPTION The AD9279 is designed for low cost, low power, small size, and ease of use for medical ultrasound and automotive radar. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), an antialiasing filter (AAF), an analog-to-digital converter (ADC), and an I/Q demodulator with programmable phase rotation. Each channel features a variable gain range of 45 dB, a fully differential signal path, an active input preamplifier termination, and a maximum gain of up to 52 dB. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical. The LNA has a single-ended-to-differential gain that is selectable through the SPI. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the LNA input SNR is roughly 94 dB. In CW Doppler mode, each LNA output drives an I/Q demod- ulator that has independently programmable phase rotation with 16 phase settings. Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo random patterns, and custom user-defined test patterns entered via the serial port interface. FUNCTIONAL BLOCK DIAGRAM AAF 12-BIT ADC VGA LNA SERIAL LVDS I/Q DEMODULATOR 8 CHANNELS SERIAL PORT INTERFACE DATA RATE MULTIPLIER REFERENCE LO GENERATION LO-A TO LO-H LOSW-A TO LOSW-H LI-A TO LI-H LG-A TO LG-H DOUTA+ TO DOUTH+ DOUTA– TO DOUTH– FCO+ DRVDD STBY PDWN AVDD2 AVDD1 FCO– DCO+ DCO– Figure 1. |
类似零件编号 - AD9279-65EBZ |
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类似说明 - AD9279-65EBZ |
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