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AD5621ACPZ-RL7 数据表(PDF) 6 Page - Analog Devices |
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AD5621ACPZ-RL7 数据表(HTML) 6 Page - Analog Devices |
6 / 24 page AD5601/AD5611/AD5621 Data Sheet Rev. G | Page 6 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. 6-Lead SC70 Pin Configuration Figure 4. 6-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions SC70 Pin No. LFCSP Pin No. Mnemonic Description 1 4 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow. The DAC is updated following the 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 2 2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 3 3 SDIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 4 1 VDD Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. 5 5 GND Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621. 6 6 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. EP Exposed Pad. Connect to GND. AD5601/ AD5611/ AD5621 TOP VIEW (Not to Scale) VOUT SYNC 1 6 GND SCLK 2 5 SDIN VDD 3 4 1 VDD 3 SDIN 2 SCLK NOTES: 1. CONNECT THE EXPOSED PAD TO GND. 6 VOUT 5 GND 4 SYNC TOP VIEW (Not to Scale) AD5601/ AD5611/ AD5621 |
类似零件编号 - AD5621ACPZ-RL7 |
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类似说明 - AD5621ACPZ-RL7 |
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