数据搜索系统,热门电子元器件搜索 |
|
AD5173BRM100 数据表(PDF) 6 Page - Analog Devices |
|
AD5173BRM100 数据表(HTML) 6 Page - Analog Devices |
6 / 24 page AD5172/AD5173 Rev. H | Page 6 of 24 TIMING CHARACTERISTICS VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted. Table 3. Parameter Symbol Conditions Min Typ Max Unit I2C INTERFACE TIMING CHARACTERISTICS1 SCL Clock Frequency fSCL 400 kHz Bus-Free Time Between Stop and Start, tBUF t1 1.3 μs Hold Time (Repeated Start), tHD;STA t2 After this period, the first clock pulse is generated. 0.6 μs Low Period of SCL Clock, tLOW t3 1.3 μs High Period of SCL Clock, tHIGH t4 0.6 μs Setup Time for Repeated Start Condition, tSU;STA t5 0.6 μs Data Hold Time, tHD;DAT2 t6 0.9 μs Data Setup Time, tSU;DAT t7 100 ns Fall Time of Both SDA and SCL Signals, tF t8 300 ns Rise Time of Both SDA and SCL Signals, tR t9 300 ns Setup Time for Stop Condition, tSU;STO t10 0.6 μs OTP Program Time t11 400 ms 1 See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 48 to Figure 51). 2 The maximum tHD;DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal. Timing Diagram t1 t2 t3 t8 t8 t9 t9 t6 t4 t7 t5 t2 t10 PS S SCL SDA P Figure 3. I2C Interface Detailed Timing Diagram |
类似零件编号 - AD5173BRM100 |
|
类似说明 - AD5173BRM100 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |