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MCZ33937AEK 数据表(PDF) 3 Page - Freescale Semiconductor, Inc

部件名 MCZ33937AEK
功能描述  Fully specified from 8.0 to 40 V covers 12 and 24 V automotive systems
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MCZ33937AEK 数据表(HTML) 3 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
3
33937A
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 33937A Pin Connections
Table 1. 33937A Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin
Pin Name
Pin Function
Formal Name
Definition
1
PHASEA
Digital Output
Phase A
Totem Pole output of Phase A comparator. This output is low when the
voltage on PA_HS_S (Source of High Side FET) is less than 50% of VSUP
2
PGND
Ground
Power Ground
Power ground for charge pump
3
EN1
Digital Input
Enable 1
Logic signal input must be high (ANDed with EN2) to enable any gate drive
output.
4
EN2
Digital Input
Enable 2
Logic signal input must be high (ANDed with EN1) to enable any gate drive
output
5
RST
Digital Input
Reset
Reset input
6, 33, 49,
50, 52, 53
N/C
No Connect
Do not connect these pins
7
PUMP
Power Drive
Out
Pump
Charge pump output
8
VPUMP
Power Input
Voltage Pump
Charge pump supply
9
VSUP
Analog Input
Supply Voltage
Supply voltage to the load. This pin is to be connected to the common
Drains of the external High Side FETs
10
PHASEB
Digital Output
Phase B
Totem Pole output of Phase B comparator. This output is low when the
voltage on PB_HS_S (Source of High Side FET) is less than 50% of VSUP
11
PHASEC
Digital Output
Phase C
Totem Pole output of Phase C comparator. This output is low when the
voltage on PC_HS_S (Source of High Side FET) is less than 50% of VSUP
54
40
.35
34
33
32
31
30
29
28
39
38
37
36
47
46
45
44
43
42
41
51
50
49
48
53
52
1
15
20
21
22
23
24
25
26
27
16
17
18
19
8
9
10
11
12
13
14
4
5
6
7
2
3
PHASEA
PGND
EN1
EN2
RST
N/C
PUMP
VPUMP
VSUP
PHASEB
PHASEC
PA_HS
PA_LS
VDD
PB_HS
PB_LS
INT
CS
SI
SCLK
SO
PC_LS
PC_HS
AMP_OUT
AMP_N
AMP_P
OC_OUT
VPWR
N/C
N/C
VLS
N/C
N/C
PA_BOOT
PA_HS_G
PA_HS_S
PA_LS_G
PA_LS_S
PB_BOOT
PB_HS_G
PB_HS_S
PB_LS_G
PB_LS_S
PC_BOOT
PC_HS_G
PC_HS_S
PC_LS_G
PC_LS_S
N/C
VLS_CAP
GND1
GND0
VSS
OC_TH
Transparent
Top View


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