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AD7846JP 数据表(PDF) 5 Page - Analog Devices

部件名 AD7846JP
功能描述  LC2MOS 16-Bit Voltage Output DAC
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7846JP 数据表(HTML) 5 Page - Analog Devices

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AD7846
Rev. G | Page 5 of 24
TIMING CHARACTERISTICS
VDD = +14.25 V to +15.75 V, VSS = −14.25 V to −15.75 V, VCC = +4.75 V to +5.25 V, unless otherwise noted.
Table 3.
Parameter1
Limit at TMIN to TMAX (All Versions)
Unit
Test Conditions/Comments
t1
0
ns min
R/W to CS setup time
t2
60
ns min
CS pulse width (write cycle)
t3
0
ns min
R/W to CS hold time
t4
60
ns min
Data setup time
t5
0
ns min
Data hold time
t62
120
ns max
Data access time
t73
10
ns min
Bus relinquish time
60
ns max
t8
0
ns min
CLR setup time
t9
70
ns min
CLR pulse width
t10
0
ns min
CLR hold time
t11
70
ns min
LDAC pulse width
t12
130
ns min
CS pulse width (read cycle)
1 Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a
voltage level of 1.6 V.
2 t6 is measured with the load circuits of Figure 3 and Figure 4 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3 t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 5 and Figure 6.
DB0
TO
DB15
5V
t3
t1
t3
DATA VALID
DATA VALID
t11
t10
LDAC
CLR
CS
R/W
0V
5V
0V
5V
0V
5V
0V
5V
0V
t10
t8
t9
t6
t1
t8
t9
t4
t5
t7
t12
t2
Figure 2. Timing Diagram
DBn
3kΩ
100pF
DGND
Figure 3. Load Circuit for Access Time (t6)—High Z to VOH
DBn
100pF
3kΩ
DGND
5V
Figure 4. Load Circuits for Bus Relinquish Time (t6)—High Z to VOL
DBn
3kΩ
10pF
DGND
Figure 5. Load Circuit for Access Time (t7)—High Z to VOH
DBn
10pF
3kΩ
DGND
5V
Figure 6. Load Circuits for Bus Relinquish Time (t7)—High Z to VOL


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