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MC145483ENR2 数据表(PDF) 8 Page - Freescale Semiconductor, Inc |
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MC145483ENR2 数据表(HTML) 8 Page - Freescale Semiconductor, Inc |
8 / 24 page Figure 2a. Long Frame Sync (Transmit and Receive Have Individual Clocking) Figure 2b. Short Frame Sync (Transmit and Receive Have Individual Clocking) Figure 2c. Sign–Extended (BCLKR = 0) Transmit and receive both use BCLKT, and the first four data bits are the sign bit. FST may occur at a different time than FSR. Figure 2d. Receive Gain Adjust (BCLKR = 1) Transmit and receive both use BCLKT. FST may occur at a different time than FSR. Bits 14, 15, and 16, clocked into DR, are used for attenuation control for the receive analog output. DR DR DON’T CARE 8 DR 7 6 5 4 3 2 1 DR DON’T CARE DON’T CARE 8 7 6 5 4 3 2 1 13 7 6 5 4 3 2 1 DT DT BCLKT FST (FSR) SHORT OR LONG FRAME SYNC DT BCLKT (BCLKR) FST (FSR) DT BCLKT (BCLKR) FST (FSR) DON’T CARE DON’T CARE DON’T CARE DON’T CARE DON’T CARE 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 16 14 13 12 11 10 9 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 910 11 12 13 8 910 11 12 13 8 9 10 11 12 13 9 10 11 12 15 16 13 8 7 6 5 4 3 2 1 12 11 10 9 BCLKT FST (FSR) SHORT OR LONG FRAME SYNC Figure 2. Digital Timing Modes for the PCM Data Interface Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
类似零件编号 - MC145483ENR2 |
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类似说明 - MC145483ENR2 |
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