FM25C640UE datasheet(3/11 Pages) FAIRCHILD

部件名	FM25C640UE

功能描述	64K-Bit SPI??Interface Serial CMOS EEPROM

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制造商	FAIRCHILD [Fairchild Semiconductor]

网页	http://www.fairchildsemi.com

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FM25C640U Rev. B

Standard Voltage 4.5

≤ V

CC ≤ 5.5V Specifications

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature

-65

°C to +150°C

All Input or Output Voltage with

Respect to Ground

+6.5V to -0.3V

Lead Temp. (Soldering, 10 sec.)

+300

°C

ESD Rating

2000V

Operating Conditions

Ambient Operating Temperature

FM25C640U

0

°C to +70°C

FM25C640UE

-40

°C to +85°C

FM25C640UV

-40

°C to +125°C

Power Supply (V

CC)

4.5V to 5.5V

DC and AC Electrical Characteristics 4.5V

≤ V

CC ≤ 5.5V (unless otherwise specified)

Symbol

Parameter

Conditions

Min

Max

Units

I

CC

Operating Current

/CS = V

IL

3mA

ICCSB

Standby Current

/CS = VCC

50

µA

I

IL

Input Leakage

V

IN = 0 to VCC

-1

+1

µA

I

OL

Output Leakage

V

OUT = GND to VCC

-1

+1

µA

VIL

CMOS Input Low Voltage

-0.3

VCC * 0.3

V

IH

CMOS Input High Voltage

0.7 * V

CC

V

CC + 0.3

V

OL

Output Low Voltage

I

OL = 1.6 mA

0.4

V

VOH

Output High Voltage

IOH = -0.8 mA

VCC - 0.8

V

f

OP

SCK Frequency

2.1

MHz

t

RI

Input Rise Time

2.0

µs

tFI

Input Fall Time

2.0

µs

t

CLH

Clock High Time

(Note 2)

190

ns

t

CLL

Clock Low Time

(Note 2)

190

ns

tCSH

Min /CS High Time

(Note 3)

240

ns

t

CSS

/CS Setup Time

240

ns

t

DIS

Data Setup Time

100

ns

tHDS

/HOLD Setup Time

90

ns

t

CSN

/CS Hold Time

240

ns

t

DIN

Data Hold Time

100

ns

tHDN

/HOLD Hold Time

90

ns

t

PD

Output Delay

C

L = 200 pF

240

ns

t

DH

Output Hold Time

0

ns

tLZ

/HOLD to Output Low Z

100

ns

t

DF

Output Disable Time

C

L = 200 pF

240

ns

t

HZ

/HOLD to Output High Z

100

ns

tWP

Write Cycle Time

1–16 Bytes

10

ms

Capacitance T

A = 25°C, f = 2.1/1 MHz (Note 4)

Symbol

Test

Typ Max Units

C

OUT

Output Capacitance

3

8

pF

C

IN

Input Capacitance

2

6

pF

AC Test Conditions

Output Load

C

L = 200 pF

Input Pulse Levels

0.1 * VCC – 0.9 * VCC

Timing Measurement Reference Level

0.3 * V

CC - 0.7 * VCC

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the

device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Note 2: The f

OP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For

example, for a f

OP of 2.1MHz, the period equals 476ns. In this case if t CLH = is set to 190ns, then tCLL must be set to a minimum of 286ns.

Note 3: /CS must be brought high for a minimum of tCSH between consecutive instruction cycles.

Note 4: This parameter is periodically sampled and not 100% tested.

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