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TSB81BA3D 数据表(PDF) 8 Page - Texas Instruments |
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TSB81BA3D 数据表(HTML) 8 Page - Texas Instruments |
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8 / 61 page  TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME TYPE NO. I/O DESCRIPTION LKON/DS2 CMOS 2 I/O Link-on output/Data-strobe-only input for port 2. This terminal may be connected to the link-on input terminal of the LLC through a 1-k Ω resistor if the link-on input is available on the link layer. Data-strobe-only mode for port 2. 1394a-only port 0 enable programming terminal. On hardware re- set, this terminal allows the user to select whether port 2 acts like a 1394b bilingual port (terminal at logic 0) or as a 1394a−2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-k Ω or less resistor to enable 1394b bilingual mode or high through a 1-kΩ or less resistor to enable 1394a−2000-only mode. A bus holder is built into this terminal After hardware reset, this terminal is the link-on output, which notifies the LLC or other power-up logic to power up and become active. The link-on output is a square wave signal with a period of approxi- mately 163 ns (8 PCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance. The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit cleared) and when one: a) The PHY receives a link-on PHY packet addressed to this node b) The PEI (port-event interrupt) register bit is 1, or c) Any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or STOI (state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1. d) The PHY is power cycled and the power class is 0 through 4 Once activated, the link-on output is active until the LLC becomes active (both the LPS input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). In the case of power cycling the PHY, the LKON signal must stop after 167 μs if the above conditions have not been met. NOTE: If an interrupt condition exists which otherwise causes the link-on output to be activated if the LLC were inactive, then the link-on output is activated when the LLC subsequently becomes inactive. LPS CMOS 80 I Link power status input. This terminal monitors the active/power status of the link-layer controller (LLC) and controls the state of the PHY-LLC interface. This terminal must be connected to either the VDD supplying the LLC through an approximately 1-kΩ resistor or to a pulsed output which is active when the LLC is powered. A pulsed signal must be used when an isolation barrier exists between the LLC and PHY (see Figure 8). The LPS input is considered inactive if it is sampled low by the PHY for more than a LPS_RESET time (~2.6 μs), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 μs). The LPS input must be high for at least 22 ns to be guaranteed to be observed as high by the PHY. When the TSB81BA3D detects that the LPS input is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D (D0 to D7) outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than a LPS_DISABLE time (~26 μs), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC state that is communicated in the self-ID packet is considered active only if both the LPS input is active and the LCtrl register bit is set to 1. The LLC state that is communicated in the self-ID packet is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. LREQ CMOS 3 I LLC request input. The LLC uses this input to initiate a service request to the TSB81BA3D. A bus holder is built into this terminal. PC0 PC1 PC2 CMOS 66 67 68 I Power class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying the terminals high through a 1-k Ω or smaller resistor or by tying directly to ground through a 1-k Ω or smaller resistor. Bus holders are built into these terminals. |
类似零件编号 - TSB81BA3D_12 |
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类似说明 - TSB81BA3D_12 |
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