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AD7927BRUZ 数据表(PDF) 4 Page - Analog Devices |
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AD7927BRUZ 数据表(HTML) 4 Page - Analog Devices |
4 / 28 page AD7927 Data Sheet Rev. C | Page 4 of 28 Parameter B Version1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V Output Low Voltage, VOL 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (Natural) Binary Coding bit set to 1 Twos Complement Coding bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 200 kSPS max See Serial Interface section POWER REQUIREMENTS AVDD 2.7/5.25 V min/max VDRIVE 2.7/5.25 V min/max IDD4 Digital inputs = 0 V or VDRIVE During Conversion 2.7 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Normal Mode (Static) 600 μA typ AVDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) fSAMPLE = 200 kSPS 1.5 mA max AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 1.2 mA max AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Using Auto Shutdown Mode fSAMPLE = 200 kSPS 900 μA typ AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz 650 μA typ AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz Auto Shutdown (Static) 0.5 μA max SCLK on or off (20 nA typ) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ) Power Dissipation4 Normal Mode (Operational) 7.5 mW max AVDD = 5 V, fSCLK = 20 MHz 3.6 mW max AVDD = 3 V, fSCLK = 20 MHz Auto Shutdown (Static) 2.5 μW max AVDD = 5 V 1.5 μW max AVDD = 3 V Full Shutdown Mode 2.5 μW max AVDD = 5 V 1.5 μW max AVDD = 3 V 1 Temperature ranges as follows: B Version: −40°C to +85°C; W Version: −40°C to +125°C. 2 See Terminology section. 3 Sample tested @ 25°C to ensure compliance. 4 See Power vs. Throughput Rate section. |
类似零件编号 - AD7927BRUZ |
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类似说明 - AD7927BRUZ |
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