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AD5640ARJ-2500RL7 数据表(PDF) 7 Page - Analog Devices |
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AD5640ARJ-2500RL7 数据表(HTML) 7 Page - Analog Devices |
7 / 28 page AD5620/AD5640/AD5660 Rev. F | Page 7 of 28 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Limit at TMIN, TMAX Parameter VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments t11 50 33 ns min SCLK cycle time t2 13 13 ns min SCLK high time t3 13 13 ns min SCLK low time t4 13 13 ns min SYNC to SCLK falling edge setup time t5 5 5 ns min Data setup time t6 4.5 4.5 ns min Data hold time t7 0 0 ns min SCLK falling edge to SYNC rising edge t8 50 33 ns min Minimum SYNC high time t9 13 13 ns min SYNC rising edge to SCLK fall ignore t10 0 0 ns min SCLK falling edge to SYNC fall ignore 1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V. DIN LSB = DB0 MSB = DB23 FOR AD5660 MSB = DB15 FOR AD5620/AD5640 SYNC SCLK MSB LSB t9 t10 t4 t3 t2 t7 t6 t5 t1 t8 Figure 2. Serial Write Operation |
类似零件编号 - AD5640ARJ-2500RL7 |
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类似说明 - AD5640ARJ-2500RL7 |
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