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AD8114AST 数据表(PDF) 6 Page - Analog Devices |
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AD8114AST 数据表(HTML) 6 Page - Analog Devices |
6 / 32 page AD8114/AD8115 Rev. B | Page 6 of 32 TIMING CHARACTERISTICS (PARALLEL) Table 4. Timing Characteristics Parameter Symbol Min Typ Max Unit Data Setup Time t1 20 ns CLK Pulse Width t2 100 ns Data Hold Time t3 20 ns CLK Pulse Separation t4 100 ns CLK to UPDATE Delay t5 0 ns UPDATE Pulse Width t6 50 ns Propagation Delay, UPDATE to Switch On or Off – 50 ns CLK, UPDATE Rise and Fall Times – 100 ns RESET Time – 200 ns Table 5. Logic Levels VIH VIL VOH VOL IIH IIL IOH IOL RESET, SER/PAR, CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3, CE, UPDATE RESET, SER/PAR, CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3, CE, UPDATE DATA OUT DATA OUT RESET, SER/PAR, CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3, CE, UPDATE RESET, SER/PAR, CLK, D0, D1, D2, D3, D4, A0, A1, A2, A3, CE, UPDATE DATA OUT DATA OUT 2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA max 3.0 mA min 1 0 1 0 D0–D3 A0–A2 CLK 1 = LATCHED UPDATE 0 = TRANSPARENT t2 t1 t5 t6 t3 t4 Figure 3. Timing Diagram, Parallel Mode |
类似零件编号 - AD8114AST |
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类似说明 - AD8114AST |
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