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AD7472YRU-REEL 数据表(PDF) 5 Page - Analog Devices |
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AD7472YRU-REEL 数据表(HTML) 5 Page - Analog Devices |
5 / 20 page REV. B –5– AD7470/AD7472 Limit at TMIN, TMAX Parameter AD7470 AD7472 Unit Description fCLK 2 10 10 kHz min 30 26 MHz max tCONVERT 436.42 531.66 ns min tCLK = 1/fCLK IN tWAKEUP 11 µs max Wake-Up Time t1 10 10 ns min CONVST Pulse Width t2 CONVST to BUSY Delay, 10 10 ns max VDD = 5 V, A and B Versions 15 ns max VDD = 5 V, Y Version 30 30 ns max VDD = 3 V, A and B Versions 35 ns max VDD = 3 V, Y Version t3 00 ns max BUSY to CS Setup Time t4 3 00 ns max CS to RD Setup Time t5 20 20 ns min RD Pulse Width t6 3 15 15 ns min Data Access Time After Falling Edge of RD t7 4 88 ns max Bus Relinquish Time After Rising Edge of RD t8 00 ns max CS to RD Hold Time t9 Acquisition Time 135 135 ns max A and B Versions 140 ns max Y Version t10 100 100 ns min Quiet Time NOTES 1Sample tested at 25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See Figure 1. 2Mark/Space ratio for the CLK inputs is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of CONVST. 3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4t 7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice. TIMING SPECIFICATIONS1 (V DD = 2.7 V to 5.25 V, REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.) 200 A IOL 200 A IOH CL 50pF TO OUTPUT PIN 1.6V Figure 1. Load Circuit for Digital Output Timing Specifications |
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