AD7607

Data Sheet

Rev. B | Page 8 of 32

Parameter

Min

Typ

Max

Unit

Description

Delay from RD falling edge to FRSTDATA low

19

ns

24

ns

17

ns

22

ns

24

ns

Delay from CS rising edge until FRSTDATA three-state enabled

1

2

The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <3 LSB performance matching between channel sets.

3

A buffer, which is equivalent to a load of 20 pF on the output pins, is used on the data output pins for these measurements.

Timing Diagrams

CONVST A,

CONVST B

CONVST A,

CONVST B

BUSY

CS

RESET

Figure 2. CONVST Timing—Reading After a Conversion

CONVST A,

CONVST B

CONVST A,

CONVST B

BUSY

CS

RESET

Figure 3. CONVST Timing—Reading During a Conversion

DATA:

DB[15:0]

FRSTDATA

CS

RD

INVALID

V1

V2

V3

V7

V8

V4

Figure 4. Parallel Mode, Separate CS and RD Pulses