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ISLA216P25 数据表(PDF) 7 Page - Intersil Corporation |
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ISLA216P25 数据表(HTML) 7 Page - Intersil Corporation |
7 / 25 page Application Note 1837 7 AN1837.0 May 3, 2013 This is set up with the source V1 at a “2” amplitude to generate the response from the input to C1 to VOUT as shown in Figure 7. The amplifier circuit is expecting a 50Ω source impedance for best flatness. The extrinsic one shown in Figure 6 will produce a 6dB loss to the board input of Figure 4 but simulating with a source set to “2” will remove that matching loss from the VOUT plot. The simulated response shows exceptional flatness down to 100kHz and about -1dB rolloff at 100MHz. That rolloff will be equalized a bit with a slight peaking in the interstage filter design. INTERSTAGE FILTER FROM THE FDA OUTPUTS TO THE ADC The signal path from the ISL55210 to the ADC is AC coupled, allowing the amplifier and ADC to operate at the common-mode voltage that optimize each device’s performance. As delivered, the differential output of the ISL55210 operate with a common mode voltage that is left to default to the internal 1.2V value. This can be adjusted to different set point via an optional path. The interstage passive circuit provides an AC coupled, 3rd order low pass filter. Built into this filter are an ADC common mode voltage servo loop which controls the common-mode DC voltage delivered to the ADC input pins and a wideband passive sense path going differential to single ended to directly measure the response shape to the ADC inputs. The circuit as delivered is shown in Figure 8. FIGURE 7. PREDICTED RESPONSE SHAPE TO VOUT FOR A 50Ω SOURCE TO THE INPUT OF C1 4 6 8 10 12 14 18 10k 1M 10M 100M 1G FREQUENCY (Hz) 16 100k 20 FIGURE 8. OUTPUT INTERFACE FROM ISL55210 TO THE ISLA214P50 DIFFERENTIAL INPUTS |
类似零件编号 - ISLA216P25 |
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类似说明 - ISLA216P25 |
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