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CD4007CM 数据表(PDF) 1 Page - Fairchild Semiconductor

部件名 CD4007CM
功能描述  Dual Complementary Pair Plus Inverter
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
标志 FAIRCHILD - Fairchild Semiconductor

CD4007CM 数据表(HTML) 1 Page - Fairchild Semiconductor

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October 1987
Revised January 1999
© 1999 Fairchild Semiconductor Corporation
DS005943.prf
www.fairchildsemi.com
CD4007C
Dual Complementary Pair Plus Inverter
General Description
The CD4007C consists of three complementary pairs of N-
and P-channel enhancement mode MOS transistors suit-
able for series/shunt applications. All inputs are protected
from static discharge by diode clamps to VDD and VSS.
For proper operation the voltages at all pins must be con-
strained to be between VSS − 0.3V and VDD + 0.3V at all
times.
Features
s Wide supply voltage range:
3.0V to 15V
s High noise immunity: 0.45 VCC (typ.)
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Note: All P-channel substrates are connected to VDD and all N-channel substrates are connected to VSS.
Top View
Order Number
Package Number
Package Description
CD4007CM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4007CN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS–001, 0.300” Wide


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