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TC58NVG0S3ETA00 数据表(PDF) 1 Page - Toshiba Semiconductor |
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TC58NVG0S3ETA00 数据表(HTML) 1 Page - Toshiba Semiconductor |
1 / 65 page TC58NVG0S3ETA00 2011-03-01C 1 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 1 GBIT (128M × 8 BIT) CMOS NAND E 2 PROM DESCRIPTION The TC58NVG0S3E is a single 3.3V 1 Gbit (1,107,296,256 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 1024blocks. The device has two 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages). The TC58NVG0S3E is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES • Organization x8 Memory cell array 2112 × 64K × 8 Register 2112 × 8 Page size 2112 bytes Block size (128K + 4K) bytes • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read • Mode control Serial input/output Command control • Number of valid blocks Min 1004 blocks Max 1024 blocks • Power supply VCC = 2.7V to 3.6V • Access time Cell array to register 25 µs max Serial Read Cycle 25 ns min (CL=100pF) • Program/Erase time Auto Page Program 300 µs/page typ. Auto Block Erase 2.5 ms/block typ. • Operating current Read (25 ns cycle) 30 mA max. Program (avg.) 30 mA max Erase (avg.) 30 mA max Standby 50 µA max • Package TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.) |
类似零件编号 - TC58NVG0S3ETA00 |
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类似说明 - TC58NVG0S3ETA00 |
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