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74F899SC 数据表(PDF) 3 Page - Fairchild Semiconductor |
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74F899SC 数据表(HTML) 3 Page - Fairchild Semiconductor |
3 / 12 page 3 www.fairchildsemi.com Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note 1: O/E = ODD/EVEN Functional Block Diagram Inputs Operation GAB GBA SEL LEA LEB H H X X X Busses A and B are 3-STATE. HL L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. H L L H H Generates parity from B[0:7] based on O/E. Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. HL L X L Generates parity from B latch data based on O/E. Generated parity → APAR. Generated parity checked against latched BPAR and output as ERRB. HL H X H BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. H L H H H BPAR/B[0:7] → APAR/A[0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. L H L H L Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. L H L H H Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. L H L L X Generates parity from A latch data based on O/E. Generated parity → BPAR. Generated parity checked against latched APAR and output as ERRA. LH H H L APAR/A[0:7] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. L H H H H APAR/A[0:7] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. |
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类似说明 - 74F899SC |
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