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74F169SC 数据表(PDF) 2 Page - Fairchild Semiconductor |
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74F169SC 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Unit Loading/Fan Out Functional Description The 74F169 uses edge-triggered J-K type flip-flops and has no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The paral- lel load operation takes precedence over other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0–P3 inputs enters the flip-flops on the next rising edge of the clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 for the 74F169 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 1. Count Enable = CEP • CET • PE 2. Up: (74F169): TC = Q 0 • Q1 • Q2 • Q3 • (Up) • CET 3. Down: TC = Q 0 • Q1 • Q2 • Q3 • (Down) • CET Mode Select Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial State Diagram Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL CEP Count Enable Parallel Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CET Count Enable Trickle Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA PE Parallel Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA U/D Up-Down Count Control Input 1.0/1.0 20 µA/−0.6 mA Q0–Q3 Flip-Flop Outputs 50/33.3 −1 mA/20 mA TC Terminal Count Output (Active LOW) 50/33.3 −1 mA/20 mA PE CEP CET U/D Action on Rising Clock Edge L X X X Load (Pn → Qn) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) |
类似零件编号 - 74F169SC |
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类似说明 - 74F169SC |
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