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74ALVC16601GX 数据表(PDF) 2 Page - Fairchild Semiconductor |
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74ALVC16601GX 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) Pin Descriptions FBGA Pin Assignments Truth Table (Note 4) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Note 4: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Note 5: Output level before the indicated steady-state input conditions were established. Note 6: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Pin Names Description OEAB, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs A1–A18 Side A Inputs or 3-STATE Outputs B1–B18 Side B Inputs or 3-STATE Outputs 12 3 4 56 A A2 A1 OEAB CLKENAB B1 B2 B A4 A3 LEAB CLKAB B3 B4 C A6 A5 VCC VCC B5 B6 D A8 A7 GND GND B7 B8 E A10 A9 GND GND B9 B10 F A12 A11 GND GND B11 B12 G A14 A13 VCC VCC B13 B14 H A16 A15 OEBA CLKBA B15 B16 J A17 A18 LEBA CLKENBA B18 B17 Inputs Outputs CLKENAB OEAB LEAB CLKAB An Bn XH X X X Z XL H X L L XL H X H H HL L X X B0 (Note 5) HL L X X B0 (Note 5) LL L ↑ LL LL L ↑ HH LL L L X B0 (Note 5) LL L H X B0 (Note 6) |
类似零件编号 - 74ALVC16601GX |
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类似说明 - 74ALVC16601GX |
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