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Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA

(Top Thru View)

Pin Descriptions

FBGA Pin Assignments

Truth Table

(Note 4)

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial (HIGH or LOW, inputs may not float)

Z

= High Impedance

Note 4: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,

LEBA, CLKBA, and CLKENBA.

Note 5: Output level before the indicated steady-state input conditions

were established.

Note 6: Output level before the indicated steady-state input conditions

were established, provided that CLKAB was HIGH before LEAB went LOW.

Pin Names

Description

OEAB, OEBA

Output Enable Inputs (Active LOW)

LEAB, LEBA

Latch Enable Inputs

CLKAB, CLKBA

Clock Inputs

CLKENAB, CLKENBA Clock Enable Inputs

Side A Inputs or 3-STATE Outputs

Side B Inputs or 3-STATE Outputs

12

3

4

56

A

OEAB CLKENAB

B

LEAB

CLKAB

C

D

GND

GND

E

GND

GND

F

GND

GND

G

H

OEBA

CLKBA

J

LEBA CLKENBA

Inputs

Outputs

CLKENAB

OEAB LEAB CLKAB

XH

X

X

X

Z

XL

H

X

L

L

XL

H

X

H

H

HL

L

X

X

HL

L

X

X

LL

L

↑

LL

LL

L

↑

HH

LL

L

L

X

LL

L

H

X