3

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Functional Description

INPUTS

Data inputs for 9-bit wide data are TTL-compatible. Word

width can be reduced by trying unused inputs to ground

and leaving the corresponding outputs open.

Reset (MR)

Reset is accomplished by pulsing the MR input LOW. Dur-

ing normal operation MR is HIGH. A reset is required after

power up to guarantee correct operation. On reset, the

data outputs go LOW, IR goes HIGH, OR goes LOW, FH

and FULL go LOW. During reset, both internal read and

write pointers are set to the first location in the array.

Shift-In (SI)

Data is written into the FIFO by pulsing SI HIGH. When

Shift-In goes HIGH, the data is loaded into an internal data

latch. Data setup and hold times need to be adhered to

with respect to the falling edge of SI. The write cycle is

complete after the falling edge of SI. The shift-in is inde-

pendent of any ongoing shift-out operation. After the first

word has been written into the FIFO, the falling edge of SI

makes HF go HIGH, indicating a non-empty FIFO. The first

data word appears at the output after the falling edge of SI.

After half the memory is filled, the next rising edge of SI

makes FULL go HIGH indicating a half-full FIFO. When the

FIFO is full, any further shift-ins are disabled.

When the FIFO is empty and OE is LOW, the falling edge

of the first SI will cause the first data word just shifted-in to

appear at the output, even though SO may be LOW.

Shift-Out (SO)

Data is read from the FIFO by the Shift-Out signal provided

the FIFO is not empty. SO going HIGH causes OR to go

LOW indicating that output stage is busy. On the falling

edge of SO, new data reaches the output after propagation

ory, OR continues to remain LOW, and the last word

shifted-out remains on the output pins.

Output Enable (OE)

OE LOW enables the 3-STATE output buffers. When OE is

HIGH, the outputs are in a 3-STATE mode.

OUTPUTS

Data outputs are enabled when OE is LOW and in the 3-

STATE condition when OE is HIGH.

Input Ready (IR)

IR HIGH indicates data can be shifted-in. When SI goes

HIGH, IR goes LOW, indicating input stage is busy. IR

stays LOW when the FIFO is full and goes HIGH after the

falling edge of the first shift-out.

Output Ready (OR)

OR HIGH indicates data can be shifted-out from the FIFO.

When SO goes HIGH, OR goes LOW, indicating output

stage is busy. OR is LOW when the FIFO is reset or empty

and goes HIGH after the falling edge of the first shift-in.

Half-Full (HF)

This status flag along with the FULL status flag indicates

the degree of fullness of the FIFO. On reset, HF is LOW; it

rises on the falling edge of the first SI. The rising edge of

the SI pulse that fills up the FIFO makes HF go LOW.

Going from the empty to the full state with SO LOW, the

falling edge of the first SI causes HF to go HIGH, the rising

edge of the 33rd SI causes FULL to go HIGH, and the ris-

ing edge of the 64th SI causes HF to go LOW.

When the FIFO is full, HF is LOW and the falling edge of

the first shift-out causes HF to go HIGH indicating a “non-

full” FIFO.

Full Flag (FULL)

This status flag along with the HF status flag indicates the

degree of fullness of the FIFO. On reset, FULL is LOW.

When half the memory is filled, on the rising edge of the

next SI, the FULL flag goes HIGH. It remains set until the

difference between the write pointer and the read pointer is

less than or equal to one-half of the total memory of the

device. The FULL flag then goes LOW on the rising edge of

the next SO.

Status Flags Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

Reset Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

HF

FULL

Status Flag Condition

L

L

Empty

L

H

Full

H

L

<32 Locations Filled

H

H

≥32 Locations Filled

Inputs

Outputs

MR

SI

SO

IR

OR

HF

FULL

H

X

X

X

X

X

X

X

L

X

X

H

L

L

L

L