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74ACTQ543QSC 数据表(PDF) 2 Page - Fairchild Semiconductor |
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74ACTQ543QSC 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 9 page www.fairchildsemi.com 2 Logic Symbols IEEE/IEC Functional Description The ACQ/ACTQ543 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A0–A7 or take data from B0–B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs Data I/O Control Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Latch Status Output Buffers CEAB LEAB OEAB H X X Latched High Z X H X Latched — L L X Transparent — XX H — High Z LX L — Driving |
类似零件编号 - 74ACTQ543QSC |
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类似说明 - 74ACTQ543QSC |
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