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2

Truth Table

H

HIGH Voltage Level steady state

h

HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition

L

LOW Voltage Level steady state

I

LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition

X

Immaterial

 LOW-to-HIGH clock transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Operating Mode

Inputs

Output

MR

CP

Reset (Clear)

L

X

X

L

Load “1”

H



hH

Load “0”

H



lL