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74ABT16543CSSC 数据表(PDF) 2 Page - Fairchild Semiconductor |
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74ABT16543CSSC 数据表(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Logic Symbol Data I/O Control Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn Functional Description The ABT16543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be low in order to enter data from the A port or take data from the B-Port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Each byte has separate con- trol inputs, allowing the device to be used as two 8-bit transceivers or as one 16-bit transceiver. Logic Diagrams Byte 1 (0:7) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Byte 2 (8:15) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Latch Status Output Buffers CEABn LEABn OEABn (Byte n) (Byte n) H X X Latched HIGH Z X H X Latched — L L X Transparent — XX H — HIGH Z L X L — Driving |
类似零件编号 - 74ABT16543CSSC |
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类似说明 - 74ABT16543CSSC |
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