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ADV473 数据表(PDF) 7 Page - Analog Devices |
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ADV473 数据表(HTML) 7 Page - Analog Devices |
7 / 12 page ADV473 –7– REV. A Table II. Address Register (ADDR) Operation Value RS2 RS1 RS0 Addressed by MPU ADDRa,b (Counts Modulo 3) 00 X 0 1 Red Value 01 X 0 1 Green Value 10 X 0 1 Blue Value ADDR0-7 (Counts Binary) 00H–FFH 0 0 1 Color Palette RAM XXXX 0000 1 0 1 Reserved XXXX 0001 1 0 1 Overlay Color 1 XXXX 0010 1 0 1 Overlay Color 2 •• • • • •• • • • XXXX 1111 1 0 1 Overlay Color 15 Overlay Color Writes The MPU writes to the address register (selecting OVERLAY REGISTER write mode, RS2 = 1, RS1 = 0 and RS0 = 0) with the address of the overlay register to be modified. The MPU performs three successive write cycles (8 or 6 bits each of red, green, and blue), using RS0–RS2 to select the Overlay Registers (RS2 = 1, RS1 = 0, RS0 = 1). After the BLUE write cycle, the three bytes of color information are concatenated into a 24-bit word or an 18-bit word and are written to the overlay register specified by the address register. The address register then in- crements to the next overlay register which the MPU may modify by simply writing another sequence of red, green, and blue data. A complete set of colors can be loaded into the over- lay registers by initially writing the start address and then per- forming a sequence of RED, GREEN and BLUE writes. The address automatically increments to the next highest location after a BLUE write. Overlay Color Reads The MPU writes to the address register (selecting OVERLAY REGISTER read mode, RS2 = 1, RS1 = 1 and RS0 = 1) with the address of the overlay register to be read back. The contents of the overlay register are copied to the RED, GREEN and BLUE registers and the address register increments to point to the next highest overlay register. The MPU then performs three successive read cycles (8 or 6 bits each of red, green, and blue), using RS0 – RS2 to select the Overlay Registers (RS2 = 1, RS1 = 0, RS0 = 1). After the BLUE read cycle, the 24/18 bit con- tents of the overlay register at the specified address register loca- tion is loaded into the RED, GREEN and BLUE registers. The address register then increments to the next overlay register which the MPU can read back by simply reading another se- quence of red, green, and blue data. A complete set of colors can be read back from the overlay registers by initially writing the start address and then performing a sequence of RED, GREEN and BLUE reads. The address automatically incremeets to the next highest location after a BLUE read. Internal Address Register (ADDR) When accessing the color palette RAM, the address register resets to 00H following a blue read or write cycle to RAM loca- tion FFH. When accessing the overlay color registers, the address register increments following a blue read or write cycle. However, while accessing the overlay color registers, the four most significant bits (since there are only 15 overlay registers) of the address register (ADDR4–7) are ignored. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table II. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other eight bits of the address register, incremented following a blue read or write cycle, (ADDR0-7) are accessible to the MPU, and are used to address color palette RAM locations and overlay registers, as shown in Table II. ADDR0 is the LSB when the MPU is access- ing the RAM or overlay registers. The MPU may read the ad- dress register at any time without modifying its contents or the existing read/write mode. Synchronization The MPU interface operates asynchronously to the pixel port. Data transfers between the color palette RAM/overlay registers and the color registers (R, G, and B as shown in the block dia- gram) are synchronized by internal logic, and occur in the pe- riod between MPU accesses. The MPU can be accessed at any time, even when the pixel CLOCK is stopped. 8-Bit/6-Bit Color Operation The Command Register on the ADV473 specifies whether the MPU is reading/writing 8 bits or 6 bits of color information each cycle. For 8-bit operation, D0 is the LSB and D7 is the MSB. For 6-bit operation, color data is contained on the lower six bits of the data bus, with D0 being the LSB and D5 the MSB of color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical “0.” It should be noted that when the ADV473 is in 6-bit mode, full- scale output current will be reduced by approximately 1.5% relative to the 8-bit mode. This is the case since the 2 LSBs of each of the three DACs are always set to zero in 6-bit mode. |
类似零件编号 - ADV473 |
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类似说明 - ADV473 |
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