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AD9203ARU 数据表(PDF) 9 Page - Analog Devices |
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AD9203ARU 数据表(HTML) 9 Page - Analog Devices |
9 / 19 page REV. 0 AD9203 REV. 0 –9– INPUT FREQUENCY – MHz 0 –1 10 1000 100 –2 –3 –4 –5 –6 –7 –8 –9 Figure 14. Full Power Bandwidth OFF-TIME – ms 3500 0 3000 2500 2000 1500 500 0 200 400 600 800 1000 1000 0.5V REFERENCE 1V REFERENCE Figure 15. Wake-Up Time vs. Off Time (VREF Decoupling = 10 µF) TEMPERATURE – C 0.2 –40 0.1 0 –0.1 –0.2 –0.3 –0.4 –20 0 20 40 60 80 100 1V 0.5V Figure 16. Reference Voltage vs. Temperature APPLYING THE AD9203 THEORY OF OPERATION The AD9203 implements a pipelined multistage architecture to achieve high sample rates while consuming low power. The AD9203 distributes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a conse- quence of the distributed conversion, the AD9203 requires a small fraction of the 1023 comparators used in a traditional 10-bit flash-type A/D. A sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Each stage of the pipeline, excluding the last, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D. The input of the AD9203 incorporates a novel structure that merges the input sample and hold amplifier (SHA) and the first pipeline residue amplifier into a single, compact switched ca- pacitor circuit. This structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline. By matching the sampling network of the input SHA with the first stage flash A/D, the AD9203 can sample inputs well beyond the Nyquist frequency with no degradation in performance. Sampling occurs on the falling edge of the clock. OPERATIONAL MODES The AD9203 may be connected in several input configurations (see Table I). The AD9203 may be driven differentially from a source that keeps the signal peaks within the power supply rails. Alternatively, the input may be driven into AINP or AINN from a single-ended source. The input span will be 2 × the programmed reference voltage. One input will accept the signal, while the opposite input will be set to midscale by connecting it to the internal or an external reference. For example, a 2 V p-p signal may be applied to AINP while a 1 V reference is applied to AINN. The AD9203 will then accept a signal varying between 2 V and 0 V. See Figures 17, 18 and 19 for more details. The AD9203’s single-ended (ac-coupled) input may also be clamped to ground by the AD9203’s internal clamp switch. This is accomplished by connecting the CLAMP pin to AINN or AINP. Digital output formats may be configured in binary and twos complement. This is determined by the potential on the DFS pin. If the pin is set to Logic “0,” the data will be in straight binary format. If the pin is asserted to Logic “1,” the data will be in twos complement format. Power consumption may be reduced by placing a resistor be- tween PWRCON and AVSS. This may be done to conserve power when not encoding high speed analog input frequencies or sampling at the maximum conversion rate. See Power Con- trol section. |
类似零件编号 - AD9203ARU |
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类似说明 - AD9203ARU |
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