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AD8345 数据表(PDF) 2 Page - Analog Devices |
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AD8345 数据表(HTML) 2 Page - Analog Devices |
2 / 16 page REV. 0 –2– AD8345–SPECIFICATIONS (V S = 5 V; LO= –2 dBm @ 800 MHz, 50 source and load impedances, I and Q inputs 0.7 V 0.3 V on each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz Baseband Frequency. TA = 25 C, unless otherwise noted.) Parameters Conditions Min Typ Max Unit RF OUTPUT Operating Frequency 1 250 1000 MHz Output Power –3 –1 +2 dBm Output P1 dB 2.5 dBm Noise Floor 20 MHz Offset from LO, All BB –155 dBm/Hz Inputs at 0.7 V Quadrature Error (CDMA IS95 Setup, Refer to Figure 13) 0.5 Degree rms I/Q Amplitude Balance (CDMA IS95 Setup, Refer to Figure 13) 0.2 dB LO Leakage –42 –33 dBm Sideband Rejection –42 –34 dBc Third Order Distortion –52 dBc Second Order Distortion –60 dBc Equivalent Output IP3 25 dBm Equivalent Output IP2 59 dBm Output Return Loss (S22) –20 dB RESPONSE TO CDMA IS95 (Refer to Figure 13) BASEBAND SIGNALS ACPR –72 dBc EVM 1.3 % Rho 0.9995 LO INPUT LO Drive level –10 –2 0 dBm LOIP Input Return Loss (S11) 2 No Termination on LOIP, LOIN at –5 dB AC Ground 50 Ω Terminating Resistor, Differential –9 dB Drive via Balun BASEBAND INPUTS Input Bias Current 10 µA Input Capacitance 2pF DC Common Level 0.6 0.7 0.8 V Bandwidth (3 dB) Full Power (0.7 V ± 0.3 V on Each 80 MHz Input, Refer to TPC 2) ENABLE Turn-On Enable High to Output within 0.5 dB of 2.5 µs Final Value Turn-Off Enable Low to Supply Current Dropping 1.5 µs below 2 mA ENBL High Threshold (Logic 1) +VS/2 V ENBL Low Threshold (Logic 0) +VS/2 V POWER SUPPLIES Voltage 2.7 5.5 V Current Active 50 65 78 mA Current Standby 70 µA NOTES 1For information on operation below 250 MHz, see Figure 4. 2See LO Drive section for more details on input matching. Specifications subject to change without notice. |
类似零件编号 - AD8345 |
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类似说明 - AD8345 |
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