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AD8108 数据表(PDF) 3 Page - Analog Devices |
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AD8108 数据表(HTML) 3 Page - Analog Devices |
3 / 28 page AD8108/AD8109 –3– REV. 0 TIMING CHARACTERISTICS (Serial) Limit Parameter Symbol Min Typ Max Units Serial Data Setup Time t1 20 ns CLK Pulsewidth t2 100 ns Serial Data Hold Time t3 20 ns CLK Pulse Separation, Serial Mode t4 100 ns CLK to UPDATE Delay t5 0ns UPDATE Pulsewidth t6 50 ns CLK to DATA OUT Valid, Serial Mode t7 180 ns Propagation Delay, UPDATE to Switch On or Off – 8 ns Data Load Time, CLK = 5 MHz, Serial Mode – 6.4 µs CLK, UPDATE Rise and Fall Times – 100 ns RESET Time – 200 ns LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE 1 0 1 0 DATA IN CLK 1 = LATCHED UPDATE 0 = TRANSPARENT DATA OUT OUT7 (D3) OUT7 (D2) OUT00 (D0) TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t1 t3 t7 t5 t6 t2 t4 Figure 1. Timing Diagram, Serial Mode Table I. Logic Levels VIH VIL VOH VOL IIH IIL IOH IOL RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR CLK, DATA IN, CLK, DATA IN, CLK, DATA IN, CLK, DATA IN, CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT 2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min |
类似零件编号 - AD8108 |
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类似说明 - AD8108 |
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