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AD807A-155BRRL7 数据表(PDF) 7 Page - Analog Devices |
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AD807A-155BRRL7 数据表(HTML) 7 Page - Analog Devices |
7 / 12 page AD807 REV. A –7– RMS JITTER – Degrees 30 0 1.4 2.3 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 25 20 15 10 5 TEST CONDITIONS WORST CASE: – 40 °C, 4.5V Figure 12. Output Jitter Histogram FREQUENCY – Hz 1E+3 100E–3 10E+0 10E+6 100E+0 1E+3 10E+3 100E+3 1E+6 100E+0 10E+0 1E+0 AD807 SONET MASK Figure 13. Jitter Tolerance NOISE – Vp-p @311MHz 3.0 0 0 0.2 0.4 0.6 0.8 1.0 2.0 1.0 PSR – NO FILTER CMR PSR – WITH FILTER 0.1 0.3 0.5 0.7 0.9 Figure 14. Output Jitter vs. Supply Noise and Output Jitter vs. Common Mode Noise THEORY OF OPERATION Quantizer The quantizer (comparator) has three gain stages, providing a net gain of 350. The quantizer takes full advantage of the Extra Fast Complementary Bipolar (XFCB) process. The input stage uses a folded cascode architecture to virtually eliminate pulse width distortion, and to handle input signals with common- mode voltage as high as the positive supply. The input offset voltage is factory trimmed and guaranteed to be less than 500 µV. XFCB’s dielectric isolation allows the different blocks within this mixed-signal IC to be isolated from each other, hence the 2 mV Sensitivity is achieved. Traditionally, high speed compara- tors are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mV. The AD807 quantizer toggles at ±650 µV (1.3 mV sensitivity) at the input without making bit errors. When the input signal is lowered below ±650 µV, circuit performance is dominated by input noise, and not crosstalk. 12 11 6 14 13 3 AVCC2 PIN NIN AVCC1 VCC1 VCC2 AD807 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 500 Ω 500 Ω 309 Ω 50 Ω 50 Ω 0.1µF 3.65k Ω 0.1µF 10µF +5V 50 Ω 311MHz NOISE INPUT 0.1µF QUANTIZER INPUT OPTIONAL FILTER FERRITE BEAD CHOKE "BIAS TEE" Figure 15. Power Supply Noise Sensitivity Test Circuit 12 11 6 14 13 3 AVCC2 PIN NIN AVCC1 VCC1 VCC2 AD807 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 500 Ω 500 Ω 309 Ω 50 Ω 50 Ω 0.1µF 3.65k Ω 10µF +5V 50 Ω 311MHz NOISE INPUT 0.1µF QUANTIZER INPUT CHOKE "BIAS TEE" Figure 16. Common-Mode Rejection Test Circuit Signal Detect The input to the signal detect circuit is taken from the first stage of the quantizer. The input signal is first processed through a gain stage. The output from the gain stage is fed to both a posi- tive and a negative peak detector. The threshold value is sub- tracted from the positive peak signal and added to the negative peak signal. The positive and negative peak signals are then compared. If the positive peak, POS, is more positive than the negative peak, NEG, the signal amplitude is greater than the threshold, and the output, SDOUT, will indicate the presence of signal by remaining low. When POS becomes more negative than NEG, the signal amplitude has fallen below the threshold, and SDOUT will indicate a loss of signal (LOS) by going high. The circuit provides hysteresis by adjusting the threshold level higher by a factor of two when the low signal level is detected. This means that the input data amplitude needs to reach twice the set LOS threshold before SDOUT will signal that the data is again valid. This corresponds to a 3 dB optical hysteresis. |
类似零件编号 - AD807A-155BRRL7 |
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类似说明 - AD807A-155BRRL7 |
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